The present invention is generally related to network switches, and more particularly to maintenance of consistency of data in segments of a distributed address cache in a network switch.
Network switches commonly employ an address cache to facilitate the flow of data units in a network. The address cache includes entries that indicate address information for various devices connected with the network such as computers and printers. In particular, the address information indicates which port or ports in the switch should be employed for forwarding the data unit to a particular device or group of devices in the network. Each data unit includes a header portion with a source address field and a destination address field. Following receipt of the data unit the switch attempts to locate an entry in the address cache that pertains to the destination address specified in the data unit header. If a pertinent entry is located in the address cache then the information contained in that entry is employed to cause transmission of the data unit via the specified port or ports associated with the address in order to "forward" the data unit toward the destination device. If a pertinent entry cannot be located in the address cache then the switch may "flood" the data unit by transmitting the data unit from every port except the port on which the data unit was received. Hence, network and switch bandwidth is conserved if a pertinent entry is available in the address cache.
It is known to update the address cache by "learning" new address information. Address information can be learned by employing the source address specified in the data unit header. If a first data unit is transmitted from a first device to a second device via the switch, and the switch does not have the address for the first device in its address cache, then upon the initial transmission from the first device to the second device the switch learns address information for the first device from the source address field of the first data unit. If address information for the second device is also unknown, the switch floods the first data unit in order to accomplish transmission to the second device. If the second device responds by transmitting a second data unit back to the first device via the switch then the switch learns the address of the second device from the source address field of the second data unit. The switch employs the learned address information for the first device to "forward" the second data unit toward the first device via a single port. In a subsequent transmission from the first device to the second device the switch employs the learned address information for the second device to efficiently "forward" the data unit toward the second device via a single port without flooding the data unit through the network.
In an effort to ensure that the address cache contains accurate address information for active data flows, unutilized entries in the address cache may be deleted in accordance with an "aging" technique. In particular, any entries that are not referenced in response to a source address search within a predetermined aging interval are deleted.
Input and output ("I/O") functions in a network switch are often implemented on Application Specific Integrated Circuits ("ASICs"). Because of limitations in the maximum practical die size, a plurality of I/O ASICs may be employed in a single network switch device. Each I/O ASIC must have access to the address cache in order to enable learning, forwarding and aging operations. One technique to provide each I/O ASIC with access to the address cache is to employ a single, centralized address cache. However, the use of a centralized address cache complicates the task of increasing the number of ports in the switch because the memory bandwidth required to support address searching increases as the number of ports increases.
One known solution to the above described problem involves the use of a distributed address cache. The distributed address cache comprises a plurality of separate cache segments, each of which is associated with one particular I/O ASIC. The use of a distributed address cache simplifies the task of increasing the number of ports in the switch because the bandwidth required for address searching is limited by the number of ports supported by each ASIC rather than the number of ports in the entire switch. However, implementing each and every learning, forwarding and aging operation is more complex when a distributed address cache is employed because different events occur simultaneously at different cache segments. Consequently, a situation will result where the segments will not each contain identical sets of entries. Such a loss of intersegment consistency has a deleterious effect on switch operation. Cache coherence algorithms can be applied to eliminate inconsistency among caches and preserve correct switch operation. Strict coherence mechanisms would require elaborate queuing methods and would impact the forwarding performance of the switch.